Low-cost high-efficiency solar: III/V-on-silicon

Speaker: 
Jordan Lang Department of Electrical Engineering, Yale University
Seminar Date: 
Friday, March 28, 2014 - 12:00pm
Location: 
BECTON SEMINAR ROOM See map
Prospect Street
New Haven, CT

Photovoltaic (PV) solar power promises to contribute significantly to the power portfolio of the 21st century by providing low-carbon direct conversion of abundant solar energy to electricity. Two significant barriers to the wide adoption of solar power currently exist: (1) low conversion efficiency and (2) high device cost. The current approach for high efficiency PV devices is a form of spectral splitting known as “multijunction,” whereby different segments of the solar spectrum are absorbed by different layers of III-V semiconductors tailored to maximize conversion efficiency. State-of-the-art multijunction devices utilize three or four junctions and have achieved record efficiencies of 44.4% under concentrated sunlight. While impressive, these devices have generally seen limited market adoption because of their high cost. The currently dominant PV semiconductor, silicon, offers decreased performance compared to multijunction technologies but at a significantly reduced cost. The low-cost of silicon PV is primarily a result of the maturity of the technology, as reflected in the saturation of device performance. The most promising method of making a disruptive change in performance while leveraging the massive scaling ability of the Si industry is to integrate a high performance III-V cell on Si to form a Si-based multijunction device, marrying high efficiency and low-cost. By growing GaAsP, a direct-bandgap III-V material, on a large-area Si wafer, substrate cost, processing cost, and manufacturing complexity can all be significantly reduced while still attaining nearly ideal dualjunction device parameters. With Si (bottom junction) having a fixed value at 1.12 eV, the tunability available in the GaAsP system (top junction) allows the growth of an ideal 1.7 eV absorber for a possible total device efficiency >35% at 1-sun and >43% under concentration, potentially transforming the economics of Si-based PV. Challenges of this approach include the necessary mitigation of extended crystal defect formation both at the GaP/Si interface (antiphase domains) and the device layers (threading dislocations). Progress in nearly ideal GaP/Si nucleation and graded buffer lattice engineering has reduced defect formation and resulted in much improved open-circuit voltage of fabricated cells. I will discuss some of the Lee Group’s recent work in this area and our approach to practical III-V/Si high-efficiency solar cells.

Host: 
Paul Fleury
Seminar Announcement Brochure: 

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